Research on Dynamic Reconfigurable Convolutional Neural Network Accelerator

The hardware implementation of convolutional neural network has the problem resource limitation, which can be solved by design accelerator based on FPGA dynamic reconstruction. whole parallel strategy and architecture CNN are designed, functional modules designed pipeline. reconstruction technology is used to redesign accelerator, region division established; BPI flash selected store configuration file, file read internally dynamically configure area. Finally, for lenet. 5 handwriting recognition, compared with corresponding static design, use slice LUTS, registers DSP resources reduced 46%, 25% 68% respectively. Compared software platform. system execution time greatly reduced. However, due bandwidth limitation internal port, reconfiguration prolongs network.